The present disclosure relates to a solid-state image pickup apparatus and a camera system which perform a vertical transfer of signal charges in a plurality of horizontal blanking periods (hereinafter, also referred to as horizontal division periods) which are obtained by dividing a horizontal period in which a horizontal transfer is performed for signal charges of one line.
In related art, for a digital camera, a solid-state image pickup element is used which forms an image of light (incident light) from a subject on an image pickup surface and outputs an image pickup signal. A CCD imager used as such a solid-state image pickup element often uses a horizontal division transfer system in order to increase a frame rate of a moving image. As a drive method for a CCD image pickup element that uses the horizontal division transfer system, a technique disclosed in Japanese Patent Application Laid-open No. 2006-310655 is known.
Generally, in a frame reading mode of the horizontal division transfer system, in one horizontal blanking period (horizontal division transfer unit), out of a plurality of parts obtained by dividing one line, a vertical transfer of signal charges is performed with the use of a vertical register. Then, when the horizontal transfer of signal charges is performed with the use of a horizontal register from a vertical register on a last stage, the transfer is performed for each horizontal division transfer unit, and then image pickup signals of one line are output.
Here, with reference to FIGS. 12 to 14, a description will be given on an example of an electrode structure and an operation timing of a CCD image pickup element in related art. It should be noted that the structure of the CCD image pickup element in related art corresponding to FIG. 12 is disclosed in Japanese Patent Application Laid-open No. 2009-290890.
FIG. 12 is an explanatory diagram showing an arrangement example of electrodes of parts that perform the horizontal transfer from the vertical transfer in the case where a horizontal 4-division transfer for 8-field reading and a vertical division transfer system are used.
The CCD image pickup element in related art controls the transfer of signal charges to the horizontal register on electrodes of Vφ1 to Vφ8 (vertical transfer clock), VφST (vertical storage control clock), VφHLD (vertical signal hold clock), φLV (vertical and horizontal shift clock), and φVOG (vertical register last stage control clock). As a result, in the horizontal register, it is possible to perform the horizontal transfer of the signal charges in multiple times. It should be noted that reference numerals (1) to (4) indicated in FIG. 12 correspond to order of columns in which the horizontal division transfer units output signal charges. Further, in the case where electrodes to which the clocks mentioned above are supplied from a timing signal generation unit (not shown) are represented, the reference numerals mentioned above are also used.
Here, columns (1) and (2) include Vφ1 to Vφ8 and Vφ1. Vφ1 on the last stage is an electrode used to make the transfer of signal charges to φLV1 or φLV2 easier. In columns not including VφST like the columns (1) and (2), if only Vφ8 is disposed under Vφ7, a gate L length (transfer length) becomes longer, with the result that it may be impossible to desirably perform the transfer of the signal charges up to φLV1. In view of this, to the last stage of the vertical register, Vφ1 is added, and thus the gate L length per electrode is suppressed.
On the other hand, columns (3) and (4) include Vφ1 to Vφ7, VφST, and VφHLD. Further, the columns (1) and (3) share φLV1 and φVOG1, and the columns (2) and (4) share φLV2 and φVOG2.
Next, the operation example of the CCD image pickup element in related art will be described.
First, signal charges accumulated in a photoelectric conversion unit are read to the vertical register in accordance with the vertical transfer clocks of Vφ1 to Vφ8. In the vertical register in the column (1), the signal charges are transferred to φLV1, and in the vertical register in the column (2), the signal charges are transferred to φLV2. On the other hand, in the vertical register in the columns (3) and (4), signal charges are accumulated in VφST.
In the column (1), by controlling φVOG1, the signal charges of φLV1 are transferred to the horizontal register, and by controlling φH1 and φH2, the signal charges are output from the horizontal register.
In the column (2), by controlling φVOG2, the signal charges of φLV2 are transferred to the horizontal register, and by controlling φH1 and φH2, the signal charges are output from the horizontal register.
If the horizontal transfer of the signal charges is performed from the columns (1) and (2), transfer control of the signal charges in the columns (3) and (4) is performed.
In the column (3), the signal charges read from VφST by controlling VφHLD are transferred to φLV1. Then, by controlling φVOG1, the signal charges of φLV1 are transferred to the horizontal register, and by controlling φH1 and φH2, the signal charges are output from the horizontal register.
In the column (4), the signal charges read from VφST by controlling VφHLD are transferred to φLV2. Then, by controlling φVOG2, the signal charges of φLV2 are transferred to the horizontal register, and by controlling φH1 and φH2, the signal charges are output from the horizontal register.
Next, a description will be given on two types of drive methods for a frame reading mode with the use of the horizontal division transfer system.
FIG. 13 is a timing chart showing an example of an HD2 uniform drive.
A drive method for performing the horizontal transfer of the signal charges with a horizontal division period being equal (or uniform) is referred to as the “HD2 uniform drive”. Here, an HD2 means a timing signal for defining a start of the horizontal division period. In performing the HD2 uniform drive, all the horizontal division periods are the same. Therefore, the length of a first horizontal division period in which the vertical transfer of signal charges of two packets is performed from a sensor unit is equal to the length of each of second to fourth horizontal division periods in each of which the horizontal transfer of signal charges is performed.
FIG. 14 is a timing chart showing an example of an HD2 reduction drive.
A drive method for performing the horizontal transfer of signal charges by reducing a horizontal division period in which the vertical transfer of signal charges read is not performed from the sensor unit is referred to as the “HD2 reduction drive”. When the HD2 reduction drive is performed, only the first horizontal division period in which the vertical transfer of signal charges of two packets is performed from the sensor unit is long, and the second to fourth horizontal division periods in each of which the vertical transfer of signal charges is not performed are short. In this case, in accordance with whether the vertical transfer is performed or not, it is possible to optimize the horizontal division periods.